Apparatus and methods providing dynamic biasing of cascode transistors in class AB amplifiers

ABSTRACT

An amplifier and method of fabricating and operating it are disclosed in which dynamically biased cascode transistors are provided in an output stage along with output transistors which are dynamically biased by differential control circuits to provide an output signal.

FIELD OF THE INVENTION

The present invention relates to class AB amplifiers, particularly to animproved output stage for such amplifiers.

BACKGROUND OF THE INVENTION

Class AB amplifiers are well known devices and have many and varieduses. One such use is as a voltage source for switching circuits where alarge amount of current is required during signal transition periods,but only a small current is required during steady state operation. Suchamplifiers have found particular utility in providing a source voltagein CMOS integrated circuit designs.

One such class AB CMOS amplifier is described in the article entitled“Class AB CMOS Amplifiers With High Efficiency” by Callewaert et al.,IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, June 1990. Thisamplifier 51, which is reproduced in FIG. 1, has an output p-channel Q30and n-channel Q27 transistors serially connected across voltage supplyterminals 23, 25, with an output 21 being taken at the interconnectionof the two transistors. The transistors Q27, Q30 are gate biased byrespective differential amplifier stages 11, 15 and associated currentsum branches 13, 17 through gate control signals developed at circuitnodes n2 and p4.

One exemplary use of the amplifier 51 is illustrated in FIG. 2 whereamplifier 51 applies an output voltage to bias capacitors 43 and 45 of asample-and-hold circuit 52 of a solid state CMOS imager device whichreads output signals from pixels 31 arranged in an array of pixel rowsand columns. The sample-and-hold circuit 52 is typically connected to acolumn line 35 to which is connected a plurality of pixel circuits 31 inparallel in respective rows of the pixel array. Column line 35 iscoupled to a current source 41. Typically two output signals areprovided by each pixel 31, a reset signal Vrst, and a signal Vsigrepresenting incident light. These signals are respectively sampledthrough sample-and-hold switches 37 and 39 controlled by control signalsSHR and SHS, respectively, to sample the reset signal Vrst on capacitor43 and the light intensity signal Vsig on capacitor 45.

Prior to the sampling operation, clamping switches 47 and 49 are closed,and a clamping voltage provided by the class AB amplifier 51 is suppliedto the back side of the capacitors. A clamp switch 48 is also typicallyprovided for equalizing the voltages supplied to the capacitors 43, 45.After switches 47, 49, and 48 are closed to provide a voltage onto theback side of capacitors 43 and 45, the switches are then opened. TheVrst signal is sampled onto the capacitor 43 and the Vsig signal issampled onto the capacitor 45. These signals are then respectivelyprovided to positive and negative inputs of operational amplifier 53,and then to one or more amplifier stages 55, and finally to ananalog-to-digital converter stage 57 where a differential analog signalVrst-Vsig representing the amount of incident light on a pixel isdigitized and used for image processing. It should be appreciated thatthere are many column lines in a CMOS imager, and that FIG. 2 representsthe circuitry associated with one column line, or circuitry which can bemultiplexed among a plurality of column lines to provide Vrst and Vsigsignals for the various pixels in a pixel array.

As further shown in FIG. 2, class AB amplifier 51 has its output 21 fedback to a negative input, while the positive input receives a referencevoltage Vref. This amplifier generally provides a very good outputvoltage during both transient periods and steady state operation.However, its operation is somewhat limited by the maximum possible gainwhich can be obtained, and the amplifier output is also sensitive topower supply noise. Power supply noise is a particular problem indigital imaging circuits, as the signal levels which are provided bypixels 31 are relatively low signal levels, so any noise in the outputprovided by class AB amplifier 51 to the back sides of capacitors 43 and45 could affect the level of signal read by the sample-and-hold circuit52 and provided ultimately to the analog-to-digital converter 57.Accordingly, an improved class AB amplifier having lower noise andimproved gain is desired.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional class AB amplifier;

FIG. 2 is a schematic diagram of one possible use for a class ABamplifier in the sample-and-hold stage of a solid state imager devicecircuit;

FIG. 3 is an electrical schematic diagram illustrating one exemplaryembodiment of the invention;

FIG. 4 is an imager device which employs the FIG. 3 embodiment of theinvention; and

FIG. 5 is a processing system which employs the imager device of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides an amplifier and methods of fabricatingand operating the same, in which the amplifier employs cascodetransistors in an output stage which provides a voltage signal foranalog and digital circuits. The cascode transistors are dynamicallybiased in accordance with operation of differential amplifier stages andassociated current sum stages employed in the amplifier.

These and other features and advantages of the invention will be betterunderstood from the following detailed description which is provided inconnection with the accompanying drawings.

FIG. 3 illustrates an exemplary embodiment of the invention. An outputstage 19′ is provided which has p-channel Q30 and N-channel Q27 outputtransistors. In addition, p-channel and n-channel cascode transistorsare also provided in the output stage 19′ as Q28 and Q29. The fourtransistors Q27, Q28, Q29, and Q30 are serially connected across voltagesupply terminals 23 and 25, which are typically connected to sourcevoltage VDD and ground respectively. An output terminal 21 is providedat the connection point between the p-channel and n-channel cascodetransistors 29 and 28.

N-channel output transistor Q27 is controlled by a first differentialamplifier stage 11′ and associated current sum branch 13′ which providean output control signal to transistor Q27 at a gate node n2. Thedifferential amplifier stage 11′ comprises a pair of p-channeldifferential transistors Q4 and Q5 respectively serially connected to apair of cascode p-channel transistors Q3 and Q6. The p-channeltransistors Q3 and Q6 are respectively serially connected to a pair ofn-channel transistors Q2 and Q7 arranged as differential inputtransistors for respectively receiving input signals vn and vp. The twodifferential input n-channel transistors Q2 and Q7 are in turn coupledtogether at a source/drain connection point which in turn is connectedto a source/drain coupled connection of n-channel bias transistors Q1and Q8. The transistor pairs Q4 and Q5, Q3 and Q6, Q2 and Q7, Q1 and Q8,are connected across the supply voltage terminals 23 and 25. A node n1provided at the gate of transistor Q1 provides a fixed bias set pointfor the differential amplifier stage 11′, and another dynamic bias setpoint is provided at an input gate node n2 to transistor Q8. As noted,the node n2 is also coupled to the gate of transistor Q27 and providesoutput control for transistor Q27. The differential amplifier stage 11′also includes an interconnection between the commonly connected gates ofp-channel transistors Q4 and Q5 to the source/drain serial connectionpoint of transistors Q3 and Q2. This connection also provides a dynamicbias point p2 which will be described later. A fixed bias point p1 isalso provided at the interconnected gates of transistors Q3 and Q6.

As noted, differential amplifier stage 11′ has an associated current sumbranch 13′ which comprises serially source/drain connected p-channeltransistors Q13, Q12, Q11, and n-channel transistors Q10 and Q9. Theserial connection of the three p-channel and two n-channel transistorsis also provided across source voltage terminals 23 and 25. Theinterconnection between p-channel transistors Q11 and Q12 is coupled tothe interconnection between the differential amplifier stage 11′transistors Q6 and Q7. The interconnection between the current sumbranch p-channel transistor Q11 and n-channel transistor Q10 is furtherconnected to the gate bias node n2 of the gate connected transistors Q8and Q9, and also to gate of the output transistor Q27 as describedabove.

The gate bias nodes p3, p4, p5 respectively associated with p-channeltransistors Q13, Q12 and Q11 receive a fixed bias potential. N-channeltransistor Q10 receives a dynamic bias potential n3 at its gate from ann-channel dynamic bias path 27 which will be described below.Transistors Q3 and Q6 of the differential amplifier stage 11′ andtransistors Q13 and Q10 of current sum branch 13′ are cascodetransistors.

P-channel output transistor Q29 is controlled by second differentialamplifier stage 15′ and associated current sum branch 17′ which providean output control signal to the gate of transistor Q29 at gate node p7.Differential amplifier stage 15′ includes a pair of gate connectedn-channel differential transistors Q14 and Q21, a pair of gate connectedcascode n-channel transistors Q15 and Q20 respectively source/drainconnected to transistors Q14, Q21 a pair of p-channel input differentialtransistors Q16 and Q19, respectively receiving differential inputs vnand vp, and which are respectively connected to transistors Q15, Q20 andwhich have commonly connected source drain terminals which are in turncommonly connected to commonly connected source/drain terminals ofp-channel transistors Q17 and Q18. Differential transistors Q14 and Q21,cascode transistors Q15 and Q20, differential input p-channeltransistors Q16 and Q19, and p-channel transistors Q17 and Q18 areserially connected as illustrated across voltage supply terminals 23 and25. The commonly connected gates of transistors Q14, Q21 are connectedto the interconnection of transistors Q15 and Q16, and also provide adynamic bias point at node n5. The gate connected transistors Q15, Q20receive a fixed bias at gate node n4.

The current sum branch 17′ includes n-channel transistors Q22, Q23 andQ24, which are serially connected through source/drain connections andfurther serially connected to serially source/drain connected p-channeltransistors Q25 and Q26. The entire current sum branch 17′, includingserially connected transistors Q22, Q23, Q24, Q25, Q26, is connectedacross voltage source terminals 23 and 25.

The interconnection of the transistors Q24 and Q23 is connected in turnto the interconnection of transistors Q20 and Q19 in the seconddifferential amplifier stage 15′. The gate of transistor Q26 isconnected to the gate of transistor Q18 in the second differentialamplifier stage 15′ and those gates are in turn commonly connected tothe interconnection between p-channel transistor Q25 and n-channeltransistor Q24. The second differential amplifier stage 15′ furtherincludes a fixed bias node p6 at the gate of transistor Q17. P-channelinput transistors Q16 and Q19 receive the same input signals vn, vp asdo the n-channel transistors Q2 and Q7 of first differential amplifierstage 11′. N-channel transistors Q22 and Q23 of current sum branch 17′receive respective fixed biases on their gate nodes n6, n7. The gatenode p8 of transistor Q25 of current sum branch 17 receives a dynamicbias from a p-channel dynamic bias circuit 29 as described in furtherdetail below.

The p-channel output transistor Q30 receives a gate input p7 controlsignal which originates at the gate connection node between p-channeltransistor Q18 from second differential amplifier stage 15′ andp-channel transistor Q26 of the current sum branch 17′.

The cascode n-channel transistor Q28 in the output stage 19′ receives adynamic bias input at node n3 from an n-channel dynamic bias circuit 27.This circuit includes an n-channel transistor Q32 having one of itssource drain terminals connected to its gate at node n3, and a pair ofparallel connected p-channel transistors Q31 and Q33, which are seriallyconnected to n-channel transistor Q32. The serial connection ofn-channel transistor Q32 and the parallel p-channel transistors Q31 andQ33 is in turn connected across source voltage terminals 23 and 25. Then3 node of n-channel dynamic bias circuit 27 provides the input gatebias for cascode n-channel transistor Q28 of the output stage 19′.

The cascode p-channel transistor Q29 of the output stage 19′ isdynamically biased by a p-channel dynamic bias circuit 29. The p-channeldynamic bias circuit 29 includes p-channel transistor Q34 having one ofits source drain terminals connected to its gate, which is seriallyconnected to a pair of parallel connected n-channel transistors Q35 andQ36. The serial connection of p-channel transistor Q34 with parallelconnected n-channel transistors Q35 and Q36 is in turn connected acrosssource voltage terminals 23 and 25. The gate node p8 of p-channeltransistor Q34 in turn supplies the dynamic bias for the gate of outputstage 19′ cascode transistor Q29.

The addition of cascode transistors Q29 and Q28 in the output stage 19′provides amplifier 51′ with an improved open loop gain response, as wellas lower noise immunity to spurious noise introduced from the powersupply supplied across terminals 23 and 25.

Additional noise immunity in the amplifier is provided by the cascodetransistors which are also provided in the first differential amplifierstage 11′ as Q3 and Q6; in the current sum branch 13′ as Q12 and Q10; inthe second differential amplifier stage 15′ as n-channel transistors Q15and Q20; and in current sum branch 17′ as transistors Q25 and Q23.

P-channel dynamic bias circuit 29 has two bias points respectively atthe gates of n-channel transistors Q35 and Q36. The gate bias node nlfor transistor Q36 is a fixed bias, while the gate bias to Q35 comesfrom node n5 which is the gate connection between transistors Q14 andQ21 of second differential amplifier stage 15′.

N-channel dynamic bias circuit 27 has two bias points respectively atthe gates of p-channel transistors Q31 and Q33. The node p6 at the gateof p-channel transistor Q33 is a fixed bias node. The gate node p2 ofp-channel channel transistor Q31 is dynamically biased by the gateinterconnected gate node p2 in first differential amplifier stage 11′.

Each of the p-channel and n-channel dynamic bias circuits 29 and 27receives a fixed bias input and a bias input which comes from firstdifferential amplifier stage 11′, for the n-channel dynamic bias stage27, and second differential amplifier stage 15′ for the p-channeldynamic bias circuit 29. Accordingly, as the first differential stage11′ operates to increase or decrease the bias to output transistor Q27at node n2, it likewise supplies a bias signal to n-channel dynamic biascircuit 27 at transistor Q31 which in turn causes n3 likewise toincrease or decrease, which increases or decreases the bias on the gateof cascode transistor 28. As a consequence, the gate bias on bothtransistors Q27 and Q28 rise and fall at the same time. Likewise, as thedifferential amplifier stage 15′ increases or decreases the outputsignal at node p7 to the gate of transistor Q30 to control the output ofp-channel transistor Q30, the p-channel dynamic bias circuit 29 receivesa bias signal at gate n5 which causes node p8 at the gate of Q34 tosupply a bias signal to the cascode transistor Q29. Accordingly, as thegate bias on output transistor Q30 rises or falls, so does the gate biasof cascode transistor Q29.

The operation of the FIG. 3 circuit in biasing the output transistorsQ30 and Q27, as well as cascode transistors Q28 and Q29 will now beexplained with reference to current paths identified in FIG. 3 as Path 0through Path 5. Operation of the FIG. 3 amplifier 51′ will be describedin connection with its use to supply a bias voltage to capacitors 43, 45in the FIG. 2 circuit. The output terminal 21 of amplifier 51′ is fedback as the input vn to the differential amplifier stages 11′, 13′, andthe input vp to both differential amplifier stages is tied to areference voltage source.

When the inputs vn, vp to the differential amplifier stages 11′ and 15′move from steady state, where vn=vp, the amplifier 51′ operates asfollows. Current Paths 0, 1 and 2 are operative when vn>vp. In thiscase, when vn>vp, more current will flow through Path 0. Since Q4 isdiode connected, it will mirror this current onto Q5. Since Q7 cannothandle this increase in current, the excess current will flow into thecurrent sum branch Path 1. This excess current is reflected to theoutput through node n2 which has its voltage increased. At the same timethat the current in Path 0 increases, it also causes the voltage on nodep2 to reduce. This drop in voltage will cause the current in path 2 toincrease, and this will also cause the voltage n3 to increase, ensuringthat transistors Q9 and Q32 stay in saturation and the differentialamplifier employed in first differential amplifier stage 11′ works well.It is noted that current paths Path 0 and 1 ensure high current gain forthe output, and current Path 2 ensures that the voltage for the cascoden-channel transistor Q28 is correctly biased during amplifier transitionperiods.

Current Paths 3, 4 and 5 are operative when the differential amplifierinputs have the signals vn≦vp. When vn≦vp, more current flows throughPath 3. Since Q14 is diode connected, Q1 will draw more current. Thiscauses an increase in current through Path 4. This excess current isreflected to the output through node p7 which biases the outputtransistor Q30. At the same time that the current through Path 3increases, and the voltage n5 increases. This increase in the voltage atn5 will cause the current in Path 5 to increase, ensuring thattransistors Q29 and Q25 remain in a saturation region. Current Paths 3and 4 ensure high current gain for the output, and Path 2 ensures thatthe cascode voltage for the cascode p-channel transistor Q29 iscorrectly biased during transition periods.

The invention also includes the fabrication of the FIG. 3 circuit as anintegrated circuit in which all stages of the amplifier 51′ describedabove are fabricated on a semiconductor substrate.

As noted, one particular utility for the FIG. 3 class AB amplifier is asa replacement for amplifier 51 illustrated in FIG. 2 which provides abias voltage to capacitors 43 and 45 through respective switches 49 and47 in the sample-and-hold circuit 52. These switches are operative priorto Vrst and Vsig being sampled on the capacitors through switches 37 and39.

The sample-and-hold circuit of FIG. 2 employing the class AB amplifier51′ illustrated in an exemplary embodiment in FIG. 3 may be used in animager device 81 depicted in FIG. 4 and may be fabricated on the samesubstrate on which imager device 81 is also fabricated. The CMOS imager81 has a pixel array 67, the readout of which is operated by a controlcircuit 65, which controls address row and column decoders 61, 71 forselecting the appropriate row and column lines for pixel readout.Control circuit 65 also controls the row and column driver circuitry 63,69 so that they apply driving voltages to the drive transistors of theselected row and column lines. As noted, the pixel output signalsinclude a pixel reset signal Vrst, readout of a pixel floating diffusionregion, after it is reset by a reset transistor and a pixel image signalVsig, which is read out of the floating diffusion region afterphoto-generated charges are transferred there. For each pixel, the Vrstand Vsig signals are sampled by the sample-and-hold circuit 73 and aresubtracted by a differential amplifier 75, to produce a differentialsignal Vrst-Vsig representing the amount of light impinging on thepixels. This difference signal is digitized by an analog-to-digitalconverter 77. The digitized pixel signals are fed to an image processor79 to form a digital image output. The digitizing and image processingcan be located on or off the imager device 81 chip. In some arrangementsthe differential signal Vrst-Vsig may be amplified as a differentialsignal and directly digitized by a differential analog-to-digitalconverter.

FIG. 5 illustrates an imaging processor system 91, for example a camerasystem, scanning system, or any other type of system for processingimages acquired by an imager device, such as imager device 81. Processorsystem 91 comprises a central processing unit (CPU) 93, such as amicroprocessor, that communicates with an input/output (I/O) device 99over one or more buses 97. The system 91 also includes an imaging device81 which may be constructed in accordance with FIG. 4 and employ theamplifier 51′ described herein. Imager 81 also communicates with the CPU93 over one or more buses 97. The processor system 91 also includesrandom access memory (RAM) 95, and can include removable memory 101 suchas flash memory, which also communicate with CPU 91, over one or morebuses 97. Imager 81 may be combined with a processor 93, such as a CPU,digital signal processor, or microprocessor, with or without memorystorage on a single integrated circuit or on a different chip than theprocessor.

While exemplary embodiments of the invention have been described andillustrated above, modifications can be made thereto without departingfrom the spirit and scope of the invention. For example, additionaln-channel or p-channel cascode transistors may be provided in the outputstage 19′, or in the differential amplifier stages 11′, 15′, the currentsum branches 13′, 17′, or in the dynamic bias circuits 27, 29. Also, theamplifier 51′ may be used in many other circuit environments than thatdescribed above. Accordingly, the foregoing description is only to beconsidered as exemplifying the invention and as not limiting thereof inany way. The invention is only limited by the scope of the claims whichare attached hereto.

1. An amplifier comprising: a pair of power supply terminals forreceiving a supply voltage; an output stage having a pair of n-channeland p-channel output transistors, and a pair of cascode n-channel andp-channel transistors, said n-channel transistors being connected inseries and said p-channel transistors being connected in series, andsaid serially connected n-channel transistors being serially connectedto said serially connected p-channel transistors; an output node in saidoutput stage at an interconnection between said n-channel and p-channeloutput transistors; a first differential amplifier stage and associatedfirst current path stage, both connected across said power supplyterminals, for biasing said n-channel output transistor; a seconddifferential amplifier stage and associated second current path stage,both connected across said power supply terminals for biasing saidp-channel output transistor; a first dynamic bias circuit coupled acrosssaid power supply terminals for biasing said n-channel cascodetransistor; and a second dynamic bias circuit coupled across said powersupply terminals for biasing said p-channel cascode transistor.
 2. Anamplifier as in claim 1, wherein said first dynamic bias stage comprisesa pair of p-channel transistors having sources and drains connected inparallel and a diode connected n-channel transistor connected in serieswith said pair of p-channel transistors, a gate connection of saidn-channel transistor providing bias to a gate of said output stagen-channel cascode transistor.
 3. An amplifier as in claim 2, wherein agate of one of said pair of p-channel transistors is connected to a biaspoint of said first differential amplifier stage and a gate of the otherof said pair of p-channel transistors is connected to receive a biaspotential applied to said second differential amplifier stage.
 4. Anamplifier as in claim 1, wherein said second dynamic bias stagecomprises a pair of n-channel transistors having source and drainsconnected in parallel and a diode connected p-channel transistorconnected in series with said pair of n-channel transistors, a gateconnection of said p-channel transistor providing bias to a gate of saidoutput stage p-channel cascode transistor.
 5. An amplifier as in claim4, wherein a gate of one of said pair of n-channel transistors isconnected to a bias point of said second differential amplifier stageand a gate of the other of said n-channel transistors is connected toreceive a bias potential applied to said first differential amplifierstage.
 6. An amplifier as in claim 2, wherein said first differentialamplifier stage and associated first current path stage, and said firstdynamic bias stage are configured such that as the gate bias on then-channel output transistor increases, the gate bias on the n-channelcascode transistor also increases.
 7. An amplifier as in claim 4,wherein said second differential amplifier stage and associated secondcurrent path stage, and said second dynamic bias stage are configuresuch that as the gate bias on the p-channel output transistor increases,the gate bias on the p-channel cascode transistor also increases.
 8. Anamplifier as in claim 1, wherein said first differential amplifier stagecomprises a differential amplifier circuit which includes cascodetransistors.
 9. An amplifier as in claim 8, wherein at least one of saidcascode transistors of said first differential amplifier state isdynamically biased.
 10. An amplifier as in claim 1, wherein said seconddifferential amplifier stage comprises a differential amplifier circuitwhich includes cascode transistors.
 11. An amplifier as in claim 10,wherein at least one of said cascode transistors of said firstdifferential amplifier state is dynamically biased.
 12. An amplifier asin claim 1, wherein said first current path stage includes cascodetransistors.
 13. An amplifier as in claim 1, wherein said second currentpath stage includes cascode transistors.
 14. An amplifier as in claim 1,wherein said first and second differential amplifier stages each receivethe same differential input, one input being coupled to said output nodeand another input being coupled to a terminal for receiving a referencevoltage.
 15. An amplifier comprising: an output stage comprising firstand second serially connected p-channel transistors and first and secondserially connected n-channel transistors, one of each of the p-channeland n-channel transistors being an output transistor, and the other ofeach of said p-channel and n-channel transistors being a cascodetransistor; an output terminal formed at a connection between saidserially connected p-channel transistors and serially connectedn-channel transistors; a first differential amplifier stage andassociated current sum branch having a control node for controlling agate of the n-channel output transistor; a second differential amplifierstage and associated current sum branch having a control node forcontrolling a gate of the p-channel output transistor; a first dynamicbias circuit for controlling the gate of said n-channel cascodetransistor in response to operation of said first differential amplifierstage; and a second dynamic bias circuit for controlling the gate ofsaid p-channel cascode transistor in response to operation of saidsecond differential amplifier stage.
 16. An amplifier comprising: anoutput stage having at least one complementary p-channel and n-channelpair of output transistors and at least one complementary p-channel andn-channel pair of cascode transistors, said transistors being seriallyconnected across source voltage terminals and providing an output at aninterconnection of a p-channel transistor and an n-channel transistor; afirst differential control circuit for controlling, in accordance with adifferential input, said at least one n-channel output transistor; asecond differential control circuit for controlling, in accordance withsaid differential input, said at least one p-channel output transistor;a third control circuit for controlling, in response to operatingconditions of said first differential control circuit, said at least onen-channel cascode transistor; and a fourth control circuit forcontrolling, in response to operating conditions of said seconddifferential control circuit, said at least one p-channel cascodetransistor.
 17. An amplifier as in claim 16 wherein said first andsecond differential control circuits receive respective first and secondinput signals as said differential input, said first differentialcontrol circuit, in response to a first input signal which exceeds asaid second input signal at said differential input, producing a firstcontrol signal which increases a gate bias applied to said n-channeloutput transistor, said fourth control circuit being responsive tocurrent path changes in said first differential control circuit whensaid first input signal exceeds said second input signal to provide asecond control signal which increases a gate bias applied to saidn-channel cascode transistor, said second differential control circuit,in response to a said second input signal which exceeds said first inputsignal at said differential amplifier, producing a third control signalwhich increases a gate bias applied to said p-channel output transistor,said third control circuit being responsive to current path changes insaid second differential control circuit when said second signal inputexceeds said first signal input to provide a fourth control signal whichincreases a gate bias applied to said p-channel cascode transistor. 18.An amplifier as in claim 16, wherein said first and second differentialamplifier stages each receive the same differential input, one inputbeing coupled to said output produced at said output stage and anotherinput being coupled to a terminal for receiving a reference voltage. 19.An amplifier comprising: an output circuit comprising serially connectedoutput and cascode p-channel transistors connected serially to seriallyconnect output and cascode n-channel transistors, said output circuithaving an output terminal at a connection point between said p-channeland n-channel transistors; and a control circuit for accepting adifferential signal input and in response thereto dynamicallycontrolling the bias applied to said output and cascode transistors ofsaid output circuit to control a voltage at said output terminal.
 19. Anamplifier as in claim 19, wherein said control circuit operates suchthat when a bias applied to said n-channel output transistor increases,a bias applied to said n-channel cascode increases, and when a biasapplied to said p-channel output transistor increases, a bias applied tosaid p-channel cascode transistor increases.
 21. An amplifier as inclaim 19, wherein said first and second differential amplifier stageseach receive the same differential input, one input being coupled tosaid output terminal and another input being coupled to a terminal forreceiving a reference voltage.
 22. An imaging device comprising: a pixelarray; a sample and hold circuit for sampling and holding pixel signalsgenerated by said array, said sample and hold circuit comprising aplurality of capacitors for holding sampled signals; and an amplifierproviding a biasing voltage to said plurality of capacitors, which isswitchable, said amplifier comprising: an output circuit comprisingserially connected output and cascode p-channel transistors connectedserially to serially connected output and cascode n-channel transistors,said output circuit having an output terminal at a connection pointbetween said p-channel and n-channel transistors; and a control circuitfor accepting a differential signal input and in response theretodynamically controlling the bias applied to said output and cascodetransistors to control a voltage at said output terminal.
 23. An imagingdevice as in claim 22, wherein said first and second differentialamplifier stages each receive the same differential input, one inputbeing coupled to said output terminal and another input being coupled toa terminal for receiving a reference voltage.
 24. An imaging device asin claim 22, wherein said control circuit operates such that when a biasapplied to said n-channel output transistor increases, a bias applied tosaid n-channel cascode increases, and when a bias applied to saidp-channel output transistor increases, a bias applied to said p-channelcascode transistor increases.
 25. An imaging device as in claim 22,wherein said control circuit comprises: an output terminal formed at aconnection between said serially connected p-channel transistors andserially connected n-channel transistors; a first differential amplifierstage and associated current sum branch having a control node forcontrolling a gate of the n-channel output transistor; a seconddifferential amplifier stage and associated current sum branch having acontrol node for controlling a gate of the p-channel output transistor;a first dynamic bias circuit for controlling the gate of said n-channelcascode transistor in response to operation of said first differentialamplifier stage; and a second dynamic bias circuit for controlling thegate of said p-channel cascode transistor in response to operation ofsaid second differential amplifier stage.
 26. A processing systemcomprising: a processor; an imaging device coupled to said processor,said imaging device comprising: a pixel array; a sample and hold circuitfor sampling and holding pixel signals generated by said array, saidsample and hold circuit comprising a plurality of capacitors for holdingsampled signals; and an amplifier for switchably providing a biasingvoltage to said plurality of capacitors, said amplifier comprising: anoutput circuit comprising serially connected output and cascodep-channel transistors connected serially to serially connected outputand cascode n-channel transistors, said output circuit having an outputterminal at a connection point between said p-channel and n-channeltransistors; and a control circuit for accepting a differential signalinput and in response thereto dynamically controlling the bias appliedto said output and cascode transistors to control a voltage at saidoutput terminal.
 27. A processing system as in claim 26, wherein saidfirst and second differential amplifier stages each receive the samedifferential input, one input being coupled to said output terminal andanother input being coupled to a terminal for receiving a referencevoltage.
 28. A processing system as in claim 26, wherein said controlcircuit operates such that when a bias applied to said n-channeltransistor increases, a bias applied to said n-channel cascodeincreases, and when a bias applied to said p-channel output transistorincreases, a bias applied to said p-channel cascode transistorincreases.
 29. A processing system as in claim 26, wherein said controlsystem comprises: an output terminal formed at a connection between saidserially connected p-channel transistors and serially connectedn-channel transistors; a first differential amplifier stage andassociated current sum branch having a control node for controlling agate of the n-channel output transistor; a second differential amplifierstage and associated current sum branch having a control node forcontrolling a gate of the p-channel output transistor; a first dynamicbias circuit for controlling the gate of said n-channel cascodetransistor in response to operation of said first differential amplifierstage; and a second dynamic bias circuit for controlling the gate ofsaid p-channel cascode transistor in response to operation of saidsecond differential amplifier stage.
 30. A method of operating anamplifier comprising: generating an output signal through an outputstage comprising a p-channel and n-channel output transistor and ap-channel and n-channel cascode transistor, said transistors beingserially connected; dynamically controlling a gate bias supplied to saidtransistors such that respective biases applied to said gates of saidn-channel transistors increase and decrease at the same time andrespective biases applied to gates of said p-channel transistorsincrease and decrease at the same time.
 31. A method as in claim 30,wherein said dynamic controlling is in response to applied differentialinput signals, one of which is taken from said output signal and anotherof which is a reference signal.
 32. A method as in claim 31, whereinsaid dynamic controlling comprises: applying a first bias signalgenerated by a first differential control circuit to a gate of saidn-channel output transistor; applying a second bias signal generated bya first dynamic bias circuit to a gate of said n-channel cascodetransistor; applying a third bias signal generated by a seconddifferential control circuit to a gate of said p-channel outputtransistor; and applying a fourth bias generated by a second dynamicbias circuit to a gate of said p-channel cascode transistor.
 33. Amethod as in claim 32, wherein said first dynamic bias circuit controlssaid second bias signal in response to changes in said firstdifferential control circuit and said second dynamic bias circuitcontrols said fourth bias signal in response to changes in said seconddifferential control circuit.
 34. A method of fabricating an integratedcircuit amplifier, said method comprising: fabricating on asemiconductor substrate an output stage having at least onecomplementary p-channel and n-channel pair of output transistors and atleast one complementary p-channel and n-channel pair of cascodetransistors, said transistors being serially connected across sourcevoltage terminals and providing an output at an interconnection of ap-channel transistor and an n-channel transistor; fabricating on saidsemiconductor substrate a first differential control circuit forcontrolling, in accordance with a differential input, said at least onen-channel out transistor; fabricating on said semiconductor substrate asecond differential control circuit for controlling, in accordance withsaid differential input, said at least one p-channel output transistor;fabricating on said semiconductor substrate a third control circuit forcontrolling, in response to operating conditions at said firstdifferential control circuit, said at least one n-channel cascodetransistor; and fabricating on said semiconductor substrate a fourthcontrol circuit for controlling, in response to operating conditions ofsaid second differential control circuit, said at least one n-channelcascode transistor.
 35. A method as in claim 34, wherein saidfabrication is such that said output is connected as a first input ofsaid differential input and a reference source terminal is a secondinput of said differential input, said fabrication further being suchthat said first differential control circuit, in response to said firstinput signal exceeding a said second input signal, produces a firstcontrol signal which increases a gate bias applied to said n-channeloutput transistor, said fourth control circuit is responsive to currentpath changes in said first differential control circuit when said firstinput exceeds said second signal to provide a second control signalwhich increases a gate bias applied to said n-channel cascodetransistor, said second differential control circuit, in response tosaid second input exceeding said first input, produces a third controlsignal which increases a gate bias applied to said p-channel outputtransistor, said third control circuit being responsive to current pathchanges in said second differential control circuit when said secondsignal input exceeds said first signal input to provide a fourth controlsignal which increases a gate bias applied to said p-channel cascodetransistor.
 36. A method of fabricating an integrated circuit amplifier,said method comprising: fabricating on a semiconductor substrate anoutput circuit comprising serially connected output and cascodep-channel transistors connected serially to serially connect output andcascode n-channel transistors, said output circuit having an outputterminal at a connection point between said p-channel and n-channeltransistors; and fabricating on said semiconductor substrate a controlcircuit for accepting a differential signal input and in responsethereto dynamically controlling the bias applied to said output andcascode transistors to control a voltage at said output terminal.
 37. Amethod as in claim 36, wherein said fabrication is such that when a biasapplied to said n-channel output transistor increases, a bias applied tosaid n-channel cascode increases, and when a bias applied to saidp-channel output transistor increases, a bias applied to said p-channelcascode transistor increases.
 38. A method of fabricating an integratedcircuit imaging device, said method comprising: fabricating on asemiconductor substrate a pixel array; fabricating on said semiconductorsubstrate a sample and hold circuit for sampling and holding pixelsignals generated by said array; and fabricating on a semiconductorsubstrate an amplifier for providing a biasing voltage to saidsample-and-hold circuit, said amplifier comprising: an output circuitcomprising serially connected output and cascode p-channel transistorsconnected serially to serially connect output and cascode n-channeltransistors, said output circuit having an output terminal at aconnection point between said p-channel and n-channel transistors; and acontrol circuit for accepting a differential signal input and inresponse thereto dynamically controlling the bias applied to said outputand cascode transistors to control a voltage at said output terminal.